1. Field of the Invention
The present invention relates to a thin film transistor array substrate, and more particularly, to a thin film transistor array substrate in a liquid crystal display device and its manufacturing method and mask used in the manufacturing method.
2. Description of the Related Art
In general, liquid crystal display (LCD) devices control light transmittance using application of an electric field to produce an image. The LCD devices commonly include a liquid crystal panel having liquid crystal cells arranged in a matrix, and a driving circuit for driving the liquid crystal cells.
The liquid crystal display panel includes a thin film transistor array substrate and an opposing color filter array substrate, wherein spacers are positioned between two substrates to maintain a constant cell gap and a liquid crystal material is provided within the cell gap. The thin film transistor array substrate commonly includes gate lines and data lines, thin film transistor switching devices at intersections of the gate lines and the data lines, pixel electrodes within liquid crystal cells defined by the crossing gate and data lines and connected to the thin film transistors, and alignment films. The gate lines and the data lines transmit signals from driving circuits via gate and data pad portions, respectively. The thin film transistors convey pixel voltages transmitted on the data lines to the pixel electrodes in response to scanning signals transmitted by the gate lines. The color filter array substrate commonly includes color filters for each of the liquid crystal cells, a black matrix that divides the color filters, a common electrode for supplying a reference voltage to the liquid crystal cells, and an alignment film.
The liquid crystal display panel is generally made by preparing the thin film array substrate and the color filter array substrate individually, joining the thin film array substrate and the color filter array substrate together, injecting a liquid crystal material between the substrates, and sealing the liquid crystal material between thin film array substrate and the color filter array substrate. Since fabricating a thin film transistor array substrate requires multiple masking processes, manufacturing a thin film transistor array substrate is significant in the production costs of a liquid crystal display panel. Accordingly, since each mask process includes many sub-processes, such as deposition, cleaning, photolithography, etching, photo-resist stripping, and inspection. Accordingly, in order to reduce production costs, significant efforts have been made to reduce the total number of required masking processes.
FIG. 1 is a partial plan view of a thin film transistor array substrate according to the related art, and FIG. 2 is a cross sectional view of the thin film transistor array substrate of FIG. 1 along I–I′ according to the related art. In FIG. 1, a thin film transistor array substrate includes crossing gate lines 2 and data lines 4 on a lower substrate 42 (in FIG. 2), wherein a gate insulating film 44 (in FIG. 2) separates the gate and data lines 2 and 4. A thin film transistor 6 is provided at each intersection, and pixel electrodes 18 are provided within liquid crystal cells defined by the gate and data lines 2 and 4. The thin film transistor array substrate includes storage capacitors 20 formed by an overlap of pixel electrodes 18 and gate lines 2. In addition, gate pad portions 26 connect to the gate lines 2, and data pad portions 34 connect to the data lines 4.
Each thin film transistor 6 includes a gate electrode 8 that is connected to a gate line 2, a source electrode 10 that is connected to a data line 4, a drain electrode 12 that is connected to a pixel electrode 18, and an active layer 14 that overlaps the gate electrode 8 to define a channel between the source electrode 10 and the drain electrode 12. The thin film transistor 6 allows a pixel voltage signal transmitted along the data line 4 to be supplied to the pixel electrode 18 and to a storage capacitor 20 in response to a gate signal transmitted along the gate line 2. In addition, the active layer 14 overlaps the data pad 36, the storage electrode 22, and the data line 4, and an ohmic contact layer 48 is provided on the active layer 14 for making ohmic contact (in FIG. 2).
In FIGS. 1 and 2, the pixel electrode 18 is connected, via a first contact hole 16 through a protective film 50, to the drain electrode 12. The pixel electrode 18 is used for producing a potential difference with respect to a common electrode (not shown) formed on the upper substrate (not shown) when charged with a pixel voltage. This potential difference rotates liquid crystals (not shown) disposed between the thin film transistor array substrate and the upper substrate (not shown) due to a dielectric anisotropy of the liquid crystals. Thus, the pixel voltage controls an amount of light transmitted through the upper substrate from a light source input positioned beneath the lower substrate 42 through the pixel electrode 18.
The storage capacitor 20 includes a portion of a “pre-stage” gate line 2. The storage capacitor 20 also includes a storage electrode 22 that overlaps the gate line 2, an interposed gate insulating film 44, an interposed active layer 14, and an interposed ohmic contact layer 48. A portion of the pixel electrode 18 disposed on the protective film 50 contacts the storage electrode 22 through a second contact hole 24 in the protective film 50. Accordingly, the storage capacitor 20 stably maintains the pixel voltage on the pixel electrode 18 until the next pixel voltage is applied.
The gate line 2 is connected, via the gate pad portion 26, to a gate driver (not shown). The gate pad portion 26 includes a gate pad 28, which extends from the gate line 2, and a gate pad protection electrode 32 that is connected, via a third contact hole 30 through the gate insulating film 44 and through the protective film 50, to the gate pad 28. The data line 4 is connected, via the data pad portion 34, to a data driver (not shown). The data pad portion 34 includes a data pad 36 that extends from the data line 4, and a data pad protection electrode 40 that is connected, via a fourth contact hole 38 through the protective film 50, to the data pad 36.
FIGS. 3A to 3D are cross sectional views illustrating a method of manufacturing the thin film transistor array substrate shown in FIG. 2 according to the related art. In FIG. 3A, a gate metal layer is formed on the upper substrate 42 by deposition, and the gate metal layer is patterned by photolithography and etching using a first mask process to form the gate line 2, the gate electrode 8, and the gate pad 28. The gate metal layer includes a single-layer or double-layer structure of chrome (Cr), molybdenum (Mo), or aluminum.
In FIG. 3B, a gate insulating film, an undoped amorphous silicon layer, an n+ amorphous silicon layer, and source/drain metal layer are sequentially provided by deposition, and a photo-resist pattern is formed on the source/drain metal layer by photolithography using a second mask, thereby forming a gate insulating film 44, an active layer 14, an ohmic contact layer 48, and source/drain patterns. In this case, a diffractive exposure mask having a diffractive exposing part at the channel region of the thin film transistor is used as a second mask. Accordingly, the photo-resist pattern at channel regions has a lower height than the remainder of the photo-resist. Subsequently, the source/drain metal layer is patterned using a wet etching process to provide source/drain patterns that include the data line 4, the source electrode 10, the drain electrode 12, which is presently integral with the source electrode 10, and the storage electrode 22.
Next, the n+ amorphous silicon layer and the amorphous silicon layer are patterned using a dry etching process and uses the same photo-resist pattern to provide the ohmic contact layer 48 and the active layer 14. The relatively low height photo-resist pattern is removed from the channel portion by an ashing process. Thereafter, the source/drain pattern and the ohmic contact layer 48 at the channel portion are etched by a wet etching process. Thus, part of the active layer 14 is exposed to disconnect the source electrode 10 from the drain electrode 12. Then, the remaining photo-resist pattern is removed by a stripping process. The gate insulating film 14 is made from an inorganic insulating material, such as silicon nitride (SiNx) or silicon oxide (SiOx), and the source/drain metal is molybdenum (Mo), titanium (Ti), tantalum (Ta), or an molybdenum alloy.
In FIG. 3C, a protective film 50 having the first through the fourth contact holes 16, 24, 30, and 38 are formed on the structure shown in FIG. 3B. The protective film 50 is provided by a deposition technique, such as plasma enhanced chemical vapor deposition (PECVD), and is then patterned by photolithography using a third mask and an etch process to define the first to the fourth contact holes 16, 24, 30, and 38. The first contact hole 16 is formed through the protective film 50 to expose a portion of the drain electrode 12. The second contact hole 24 is formed through the protective film 50 to expose a portion the storage electrode 22. The third contact hole 30 is formed through the protective film 50 and through the gate insulating film 44 to expose a portion of the gate pad 28. The fourth contact hole 38 is formed through the protective film 50 to expose a portion of the data pad 36. The protective film 50 is made from an inorganic material that is identical to the gate insulating film 44, or from an organic material having a small dielectric constant, such as an acrylic organic compound, BCB(benzocyclobutene) or PFCB(perfluorocyclobutane).
In FIG. 3D, transparent electrode patterns are provided on the protective film 50. A transparent electrode material is deposited onto the structure shown in FIG. 3C using a deposition technique, such as sputtering. Then, the transparent electrode material is patterned by photolithography using a fourth mask and an etching process to provide the transparent electrode patterns. That pattern includes the pixel electrode 18, the gate pad protection electrode 32, and the data pad protection electrode 40, wherein the pixel electrode 18 is electrically connected via the first contact hole 16 to the drain electrode 12, and to the storage electrode 22 via the second contact hole 24. In addition, the pixel electrode 18 overlaps part of the pre-stage gate line 2, the gate pad protection electrode 32 is electrically connected via the third contact hole 30 to the gate pad 28, and the data pad protection electrode 40 is electrically connected via the fourth contact hole 38 to the data pad 36. The transparent electrode material comprises indium-tin-oxide (ITO), tin-oxide (TO), or of indium-zinc-oxide (IZO).